US 11,955,527 B2
Nano transistors with source/drain having side contacts to 2-D material
Chao-Ching Cheng, Hsinchu (TW); Yi-Tse Hung, Hsinchu (TW); Hung-Li Chiang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); Lain-Jong Li, Hsinchu (TW); and Jin Cai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 18, 2021, as Appl. No. 17/351,622.
Claims priority of provisional application 63/107,041, filed on Oct. 29, 2020.
Prior Publication US 2022/0140098 A1, May 5, 2022
Int. Cl. H01L 29/00 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/2003 (2013.01); H01L 29/66446 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first sacrificial layer over a substrate;
forming a sandwich structure over the first sacrificial layer, wherein the sandwich structure comprises a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material;
forming a second sacrificial layer over the sandwich structure;
forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material;
removing the first sacrificial layer and the second sacrificial layer to generate spaces; and
forming a gate stack filling the spaces.