US 11,955,521 B1
Manufacturable thin film gallium and nitrogen containing devices
James W. Raring, Santa Barbara, CA (US); Melvin McLaurin, Santa Barbara, CA (US); Alexander Sztein, Santa Barbara, CA (US); and Po Shan Hsu, Arcadia, CA (US)
Assigned to KYOCERA SLD Laser, Inc., Goleta, CA (US)
Filed by KYOCERA SLD Laser, Inc., Goleta, CA (US)
Filed on Oct. 23, 2020, as Appl. No. 17/078,389.
Application 17/078,389 is a continuation of application No. 16/835,082, filed on Mar. 30, 2020, granted, now 10,854,778.
Application 16/835,082 is a continuation of application No. 16/796,154, filed on Feb. 20, 2020, granted, now 10,854,776.
Application 16/796,154 is a continuation of application No. 16/005,255, filed on Jun. 11, 2018, granted, now 10,629,689, issued on Apr. 21, 2020.
Application 16/005,255 is a continuation of application No. 15/480,239, filed on Apr. 5, 2017, granted, now 10,002,928, issued on Jun. 19, 2018.
Application 15/480,239 is a continuation of application No. 15/209,309, filed on Jul. 13, 2016, granted, now 9,653,642, issued on May 16, 2017.
Application 15/209,309 is a continuation in part of application No. 14/580,693, filed on Dec. 23, 2014, granted, now 9,666,677, issued on May 30, 2017.
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/205 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/683 (2006.01); H01L 21/8252 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 27/15 (2006.01); H01L 29/66 (2006.01); H01L 33/00 (2010.01); H01L 33/06 (2010.01); H01L 33/32 (2010.01); H01S 5/02 (2006.01); H01S 5/227 (2006.01); H01S 5/343 (2006.01); H01L 21/8258 (2006.01); H01L 27/085 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/43 (2006.01); H01L 29/778 (2006.01); H01L 29/861 (2006.01); H01L 29/872 (2006.01)
CPC H01L 29/205 (2013.01) [H01L 21/02458 (2013.01); H01L 21/311 (2013.01); H01L 21/6835 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 27/0629 (2013.01); H01L 27/0676 (2013.01); H01L 27/088 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 27/15 (2013.01); H01L 29/66136 (2013.01); H01L 29/66143 (2013.01); H01L 29/66318 (2013.01); H01L 29/66462 (2013.01); H01L 29/66916 (2013.01); H01L 33/0025 (2013.01); H01L 33/0066 (2013.01); H01L 33/007 (2013.01); H01L 33/0075 (2013.01); H01L 33/0093 (2020.05); H01L 33/06 (2013.01); H01L 33/32 (2013.01); H01S 5/0203 (2013.01); H01S 5/0217 (2013.01); H01S 5/227 (2013.01); H01S 5/34333 (2013.01); H01L 21/8258 (2013.01); H01L 27/085 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/432 (2013.01); H01L 29/7786 (2013.01); H01L 29/8613 (2013.01); H01L 29/872 (2013.01); H01L 2224/95 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A partially completed semiconductor device for processing, comprising:
a plurality of dies arranged in an array and overlying a surface region of a substrate, each of the plurality of dies comprising an epitaxial material, the epitaxial material comprising a release material overlying the substrate and at least an intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material or at least an n-type gallium and nitrogen containing region overlying the release material or at least a p-type gallium and nitrogen containing region overlying the release material or at least a combination of one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material, wherein adjacent ones of the plurality of dies in the array are separated by a first pitch;
interface regions overlying the epitaxial material of the plurality of dies, each of the interface regions comprising a metal, a semiconductor, dielectric, oxide, glass, or a polymer, wherein at least a portion of the interface regions are bonded to a carrier wafer to form a bonded structure;
wherein the plurality of dies provided on the substrate are releasable to transfer at least the portion of the plurality of dies to the carrier wafer, wherein adjacent pairs of the transferred dies are configured with a second pitch on the carrier wafer, the second pitch being equal to or greater than the first pitch.