US 11,955,516 B2
Method for manufacturing a semiconductor device
Ho-Jun Kim, Suwon-si (KR); Woong Sik Nam, Seoul (KR); and Mirco Cantoro, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 27, 2023, as Appl. No. 18/102,204.
Application 18/102,204 is a continuation of application No. 17/333,080, filed on May 28, 2021, granted, now 11,569,349.
Claims priority of application No. 10-2020-0139044 (KR), filed on Oct. 26, 2020.
Prior Publication US 2023/0163171 A1, May 25, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 21/823481 (2013.01); H01L 29/4236 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a plurality of active patterns extending in a first direction on the substrate;
forming a pre-gate structure extending in a second direction and intersecting the plurality of active patterns, the pre-gate structure including a pre-gate electrode, a pre-gate spacer, and a pre-gate capping pattern on the pre-gate electrode;
forming a gate separation trench by partially removing the pre-gate electrode, the pre-gate spacer, and the pre-gate capping pattern, a connecting spacer being formed by partially removing the pre-gate spacer; and
forming a gate separation structure filling the gate separation trench, the gate separation structure including a gate separation liner and a gate separation filling film on the gate separation liner, the gate separation liner of the gate separation structure extending along a top surface and sidewalls of the connecting spacer and contacting the connecting spacer, and a topmost surface of the gate separation liner and a top surface of the pre-gate capping pattern being on a same plane.