	US 11,955,515 B2
	Dual side contact structures in semiconductor devices
Shih-Chuan Chiu, Hsinchu (TW); Chia-Hao Chang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Chih-Hao Wang, Baoshan Township (TW); Huan-Chieh Su, Tianzhong Township (TW); Chun-Yuan Chen, Hsinchu (TW); Li-Zhen Yu, New Taipei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2022, as Appl. No. 17/815,761.
Application 17/815,761 is a continuation of application No. 17/238,983, filed on Apr. 23, 2021, granted, now 11,482,595.
Prior Publication US 2023/0008614 A1, Jan. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01)

CPC H01L 29/0673 (2013.01) [H01L 21/823418 (2013.01); H01L 29/42392 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

a substrate;

first and second nanostructured channel regions disposed on the substrate;

first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively;

first and second source/drain (S/D) regions disposed on the substrate;

first and second contact structures disposed on first surfaces of the first and second S/D regions, respectively;

a third contact structure comprising an n-type work function metal (nWFM) silicide layer disposed on a second surface of the first S/D region and a dual metal liner disposed on the nWFM silicide layer; and

a fourth contact structure comprising a p-type WFM (pWFM) silicide layer disposed on a second surface of the second S/D region.