US 11,955,514 B2
Field-effect transistors with a gate structure in a dual-depth trench isolation structure
Bong Woong Mun, Singapore (SG); and Jeoung Mo Koo, Singapore (SG)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed on Jun. 1, 2021, as Appl. No. 17/335,093.
Prior Publication US 2022/0384571 A1, Dec. 1, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/66681 (2013.01); H01L 29/7816 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate having an upper surface;
a source region in the substrate;
a drain region in the substrate;
a trench isolation structure in the substrate between the source region and the drain region, the trench isolation structure having a first portion with a first lower surface and a second portion with a second lower surface below the first lower surface of the first portion, the second portion is connected to the first portion and in contact with the drain region, wherein the first portion and the second portion of the trench isolation structure comprise the same dielectric material; and
a gate structure in the substrate adjacent to the trench isolation structure.