US 11,955,512 B1
Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication
Somilkumar J. Rathi, San Jose, CA (US); Noriyuki Sato, Hillsboro, OR (US); Niloy Mukherjee, San Ramon, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Tanay Gosavi, Portland, OR (US); Pratyush Pandey, Kensington, CA (US); Jason Y. Wu, Albany, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,266.
Application 17/552,266 is a continuation of application No. 17/550,899, filed on Dec. 14, 2021.
Int. Cl. H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/91 (2013.01) [H01L 21/3212 (2013.01); H01L 21/76843 (2013.01); H01L 28/92 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating a device structure, the method comprising:
forming an electrode structure in a memory region by a first process comprising:
etching a first opening in an etch stop layer and exposing a first conductive interconnect below the etch stop layer;
depositing a first conductive hydrogen barrier layer in the first opening; and
depositing a first conductive material on the first conductive hydrogen barrier layer;
depositing a first dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the electrode structure;
forming a trench capacitor by a second process comprising:
forming a trench in the first dielectric, the trench exposing at least a portion of the electrode structure;
depositing a first electrode layer on a base and on sidewalls of the trench;
depositing a dielectric layer comprising a ferroelectric material or a paraelectric material on the first electrode layer; and
depositing a second electrode layer on the dielectric layer;
depositing a second dielectric comprising a less than 90% film density material on the etch stop layer in an adjacent logic region;
forming a via electrode on the trench capacitor by a third process comprising:
depositing a second conductive hydrogen barrier layer on the second electrode layer; and
depositing a second conductive material on the second conductive hydrogen barrier layer;
forming a second opening in the second dielectric and in the etch stop layer; and
depositing a conductive material in the second opening to form a via structure on a second conductive interconnect.