US 11,955,500 B2
Solid-state imaging device and electronic apparatus
Reijiroh Shohji, Tokyo (JP); Masaki Haneda, Kanagawa (JP); Hiroshi Horikoshi, Tokyo (JP); Minoru Ishida, Tokyo (JP); Takatoshi Kameshima, Kanagawa (JP); Ikue Mitsuhashi, Kanagawa (JP); Hideto Hashiguchi, Kanagawa (JP); and Tadashi Iijima, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Feb. 3, 2022, as Appl. No. 17/592,025.
Application 17/592,025 is a continuation of application No. 16/497,084, granted, now 11,289,526, previously published as PCT/JP2018/011565, filed on Mar. 23, 2018.
Claims priority of application No. 2017-074807 (JP), filed on Apr. 4, 2017; and application No. 2017-130384 (JP), filed on Jul. 3, 2017.
Prior Publication US 2022/0157877 A1, May 19, 2022
Int. Cl. H01L 27/146 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 27/14634 (2013.01); H01L 2224/08145 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a first substrate, including:
a first semiconductor substrate including a plurality of pixels;
a first multi-layered wiring layer stacked on the first semiconductor substrate; and
a first electrode included in the first multi-layered wiring layer;
a second substrate, including:
a second semiconductor substrate;
a second multi-layered wiring layer stacked on the second semiconductor substrate;
a second electrode included in the second multi-layered wiring layer;
an insulating layer on a second side of the second semiconductor substrate, wherein the second substrate is stacked on the first substrate such that the first multi-layered wiring layer and the second multi-layered wiring layer are opposed to each other;
a third electrode included in the insulating layer; and
a via, wherein the via extends from the second multi-layered wiring layer, through the second semiconductor substrate and to the insulating layer, and
wherein the via is electrically connected to the third electrode; and
a third substrate, including:
a third semiconductor substrate;
a third multi-layered wiring layer stacked on the third semiconductor substrate; and
a fourth electrode included in the third multi-layered wiring layer, wherein the third substrate is stacked on the second substrate such that the insulating layer and the third multi-layered wiring layer are opposed to each other,
wherein the first substrate and the second substrate are electrically connected by a direct contact between the first electrode and the second electrode at a bonding surface between the first substrate and the second substrate,
wherein the second substrate and the third substrate are electrically connected by a direct contact between the third electrode and the fourth electrode at a bonding surface between the second substrate and the third substrate,
wherein, in a plan view, at least a part of the via overlaps at least a part of the third electrode and at least a part of the fourth electrode, and
wherein the third substrate includes a logic circuit.