US 11,955,487 B2
Semiconductor device
Yoon Tae Hwang, Seoul (KR); Sunjung Lee, Suwon-si (KR); Heonbok Lee, Suwon-si (KR); Geunwoo Kim, Seoul (KR); and Wandon Kim, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 12, 2022, as Appl. No. 17/886,878.
Application 17/886,878 is a continuation of application No. 16/898,719, filed on Jun. 11, 2020, granted, now 11,417,656.
Claims priority of application No. 10-2019-0122554 (KR), filed on Oct. 2, 2019.
Prior Publication US 2022/0392899 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
semiconductor patterns vertically stacked on a substrate;
a gate electrode extended in a first direction to fill a space between the semiconductor patterns;
a source/drain pattern disposed at a side of the gate electrode and connected to the semiconductor patterns;
an interlayer insulating layer covering the gate electrode and the source/drain pattern;
a contact plug including a first portion, which is buried in the source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion;
an interface layer between the first portion and the source/drain pattern; and
a metal oxide between the second portion and the interlayer insulating layer,
wherein the interlayer insulating layer covers a portion of a top surface of the first portion.