US 11,955,484 B2
Semiconductor device and manufacturing method thereof
Kuan-Jung Chen, Tainan (TW); I-Chih Chen, Tainan (TW); Chih-Mu Huang, Tainan (TW); Kai-Di Wu, Tainan (TW); Ming-Feng Lee, Chiayi County (TW); and Ting-Chun Kuan, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 10, 2022, as Appl. No. 17/837,046.
Application 17/837,046 is a continuation of application No. 16/151,329, filed on Oct. 3, 2018, granted, now 11,404,413.
Claims priority of provisional application 62/583,452, filed on Nov. 8, 2017.
Prior Publication US 2022/0302110 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/1037 (2013.01); H01L 29/42372 (2013.01); H01L 29/66545 (2013.01); H01L 29/66818 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a first region and a second region, wherein the first region comprises a first semiconductor fin and the second region comprises a second semiconductor fin, a width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin, a width of a middle portion of the second semiconductor fin is different from widths of end portions of the second semiconductor fin, a dopant of the first semiconductor fin and the second semiconductor fin comprises boron, BF2, phosphorus, arsenic, or a combination thereof, a dopant concentration within the first semiconductor fin ranges from 2×1011 atom/cm2 to 1×1012 atom/cm2 and a dopant concentration within the first semiconductor fin is less than the dopant concentration within the second semiconductor fin;
a plurality of gate stacks over a portion of the first semiconductor fin and a portion of the second semiconductor fin;
a first S/D covering another portion of the first semiconductor fin; and
a second S/D covering another portion of the second semiconductor fin.