US 11,955,479 B2
Packaged semiconductor device
Yiqi Tang, Allen, TX (US); Rajen Manicon Murugan, Dallas, TX (US); and Makarand Ramkrishna Kulkarni, Dallas, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 29, 2019, as Appl. No. 16/667,051.
Application 16/667,051 is a continuation of application No. 16/037,695, filed on Jul. 17, 2018, granted, now 10,475,786.
Claims priority of provisional application 62/675,396, filed on May 23, 2018.
Prior Publication US 2020/0066716 A1, Feb. 27, 2020
Int. Cl. H01L 27/07 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H05K 1/02 (2006.01)
CPC H01L 27/0733 (2013.01) [H01L 23/3128 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H05K 1/0231 (2013.01); H01L 2924/15311 (2013.01); H05K 2201/09118 (2013.01)] 43 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a multi-layer molded interconnect substrate (MIS) having a signal layer including first and second traces for a first channel and first and second traces for a second channel on a dielectric layer with vias, wherein the first and second traces of the first and second channels include narrowed trace regions and a bottom metal layer comprises a patterned layer including a plurality of ground cut regions, at least one of the first and second traces for the first channel and the first and second traces for the second channel being over one of the ground cut regions.