| CPC H01L 27/0629 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device comprising:
forming a stack including a plurality of alternately stacked sacrificial layers and a plurality of channel layers on a resistor region and a transistor region of a substrate, the resistor region including an active region in an N well region;
forming, in the resistor region, a first trench in an upper portion of the substrate and forming a first device isolation layer in the first trench;
forming, in the transistor region, a second trench in the upper portion of the substrate and forming a second device isolation layer in the second trench;
forming, in the resistor region, a third trench in the upper portion of the substrate and forming a buried insulating layer in the third trench, the buried insulating layer dividing the active region into a first active region and a second active region extending in a first horizontal direction;
forming, in the resistor region, first dummy gate structures extending in a second horizontal direction crossing the first horizontal direction on the stack, each of the first dummy gate structures including a first dummy gate electrode and first gate spacers on side surfaces of the first dummy gate electrode;
forming, in the transistor region, a second dummy gate structure extending in the second horizontal direction on the stack, the second dummy gate structure including a second dummy gate electrode and second gate spacers on side surfaces of the second dummy gate electrode;
forming, in the resistor region, a first doped region and a second doped region each disposed on side surfaces of the first dummy gate structures on the first active region and the second active region;
forming, in the transistor region, a source/drain region on side surfaces of the second dummy gate structure;
removing the first dummy gate electrodes and forming first gate electrodes in a space where the first dummy gate electrodes are removed; and
removing the second dummy gate electrode and forming a second gate electrode in a space where the second dummy gate electrode is removed,
wherein the first doped region and the second doped region is in contact with the N well region and including n impurities.
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