US 11,955,474 B2
Semiconductor layout for electrostatic discharge protection, electrostatic discharge protection circuit, and method for forming the same
Fang-Wen Liu, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Aug. 22, 2022, as Appl. No. 17/892,797.
Prior Publication US 2024/0063214 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0288 (2013.01) [H01L 27/0266 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01); H02H 9/045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor layout used for electrostatic discharge (ESD) protection, the semiconductor layout comprising:
a core circuit;
a MOS transistor, configured to protect the core circuit by dispersing an ESD current thereacross during an ESD event;
a dummy structure, arranged between the MOS transistor and the core circuit, wherein the dummy structure comprises at least one of a poly layer and a metal layer; and
a resistor, overlapping the dummy structure and adjacent to the MOS transistor, wherein the resistor comprises a portion of the at least one of the poly layer and the metal layer.