US 11,955,473 B2
Semiconductor device, display device, and electronic apparatus
Yutaka Kobashi, Fujimichou (JP)
Assigned to 138 East LCD Advancements Limited, Dublin (IE)
Filed by 138 East LCD Advancements Limited, Dublin (IE)
Filed on Jun. 13, 2022, as Appl. No. 17/838,477.
Application 17/838,477 is a continuation of application No. 17/188,424, filed on Mar. 1, 2021, granted, now 11,362,081.
Application 17/188,424 is a continuation of application No. 16/242,709, filed on Jan. 8, 2019, granted, now 10,937,779, issued on Mar. 2, 2021.
Application 16/242,709 is a continuation of application No. 14/564,759, filed on Dec. 9, 2014, granted, now 10,181,462, issued on Jan. 15, 2019.
Application 14/564,759 is a continuation of application No. 12/436,335, filed on May 6, 2009, granted, now 9,184,157, issued on Nov. 10, 2015.
Application 12/436,335 is a continuation of application No. 11/101,450, filed on Apr. 8, 2005, granted, now 7,755,875, issued on Jul. 13, 2010.
Claims priority of application No. 2004-198040 (JP), filed on Jul. 5, 2004.
Prior Publication US 2022/0310588 A1, Sep. 29, 2022
Int. Cl. H01L 27/02 (2006.01); G02F 1/1362 (2006.01); G09G 3/3208 (2016.01); G09G 3/3225 (2016.01); G09G 3/36 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/0251 (2013.01) [G02F 1/136204 (2013.01); G09G 3/3208 (2013.01); G09G 3/3225 (2013.01); G09G 3/36 (2013.01); G09G 3/3648 (2013.01); H01L 27/1214 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0819 (2013.01); G09G 2330/04 (2013.01); H01L 27/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
an active matrix arranged on the substrate;
a driving circuit arranged along a first side of the substrate in a peripheral area that surrounds the active matrix;
in the peripheral area, a first signal line having a first end that is connected between a first terminal and a first end of the driving circuit, the first signal line supplying a first driving signal to the driving circuit;
a first protective circuit arranged in the peripheral area and connected between the first end of the first signal line and the first end of the driving circuit;
a second protective circuit arranged in the peripheral area and connected between a second end of the driving circuit and a second end of the first signal line;
in the peripheral area, a first power line having a third end that is connected between a second terminal and the first end of the driving circuit, the first power line supplying a first driving voltage to the driving circuit;
a third protective circuit arranged in the peripheral area and connected between the third end of the first power line and the first end of the driving circuit; and
a fourth protective circuit arranged in the peripheral area and connected between the second end of the driving circuit and a fourth end of the first power line,
wherein the driving circuit is connected between the first protective circuit and the second protective circuit, and
wherein the driving circuit is connected between the third protective circuit and the fourth protective circuit.