US 11,955,470 B2
Semiconductor device and electronic system
Jiwon Kim, Seoul (KR); Jaeho Ahn, Seoul (KR); Sungmin Hwang, Hwaseong-si (KR); Joonsung Lim, Seongnam-si (KR); and Sukkang Sung, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 13, 2021, as Appl. No. 17/229,062.
Claims priority of application No. 10-2020-0126370 (KR), filed on Sep. 28, 2020.
Prior Publication US 2022/0102334 A1, Mar. 31, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 24/08 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2224/08147 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first peripheral circuit region comprising a plurality of lower circuitries;
a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries; and
a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction, such that a lower surface of the cell region is on an upper surface of the first peripheral circuit region and lower surface of the second peripheral circuit region is on an upper surface of the cell region,
wherein the plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.