US 11,955,467 B2
Semiconductor device and method of forming vertical interconnect structure for PoP module
Junghwan Jang, Incheon (KR); Giwoong Nam, Incheon (KR); and Myongsuk Kang, Incheon (KR)
Assigned to STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed by STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed on Jun. 14, 2021, as Appl. No. 17/347,065.
Prior Publication US 2022/0399315 A1, Dec. 15, 2022
Int. Cl. H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first light sensitive material over the substrate;
forming a plurality of first conductive posts over the substrate by patterning the first light sensitive material and filling the pattern with conductive material;
disposing a first electrical component over the substrate between the first conductive posts;
depositing a first encapsulant over the first electrical component and conductive posts;
removing a portion of the first encapsulant to expose the first conductive posts; and
singulating through the first conductive posts to expose a side surface of the first conductive posts, wherein the exposed side surface of the first conductive posts extends between a first surface of the first encapsulant and a second surface of the first encapsulant opposite the first surface of the first encapsulant.