US 11,955,460 B2
Advanced info POP and method of forming thereof
Yi-Da Tsai, Dongshi Township (TW); Meng-Tse Chen, Changzhi Township (TW); Sheng-Feng Weng, Taichung (TW); Sheng-Hsiang Chiu, Tainan (TW); Wei-Hung Lin, Xinfeng Township (TW); Ming-Da Cheng, Taoyuan (TW); Ching-Hua Hsieh, Hsinchu (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Oct. 5, 2020, as Appl. No. 17/063,251.
Application 17/063,251 is a division of application No. 15/157,192, filed on May 17, 2016, granted, now 10,797,025.
Prior Publication US 2021/0020611 A1, Jan. 21, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 24/17 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/024 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/06 (2013.01); H01L 2924/0635 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/07025 (2013.01); H01L 2924/0715 (2013.01); H01L 2924/14 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19102 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package-on-package (PoP) structure comprising:
a first semiconductor package having a first side, a second side opposing the first side, and external connectors at the second side of the first semiconductor package;
a second semiconductor package having a third side and a fourth side opposing the third side, wherein the fourth side of the second semiconductor package faces the first side of the first semiconductor package;
inter-package connectors coupled between the first side of the first semiconductor package and the fourth side of the second semiconductor package; and
a first molding material, wherein the first molding material is disposed between the first semiconductor package and the second semiconductor package, and extends along the second side of the first semiconductor package, wherein the third side of the second semiconductor package is free of the first molding material, wherein a coefficient of thermal expansion (CTE) of the first molding material is between a first overall CTE of the first semiconductor package and a second overall CTE of the second semiconductor package.