US 11,955,458 B2
Semiconductor package
Sangkil Lee, Suwon-si (KR); So-young Kim, Suwon-si (KR); and Soo-woong Ahn, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 17, 2023, as Appl. No. 18/318,975.
Application 18/318,975 is a continuation of application No. 17/576,440, filed on Jan. 14, 2022, granted, now 11,688,719.
Application 17/576,440 is a continuation of application No. 16/689,769, filed on Nov. 20, 2019, granted, now 11,251,155, issued on Feb. 15, 2022.
Claims priority of application No. 10-2019-0063579 (KR), filed on May 30, 2019.
Prior Publication US 2023/0290754 A1, Sep. 14, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a logic die provided on an interposer substrate; and
a memory stack structure provided adjacent to the logic die,
wherein the memory stack structure comprises:
a buffer die provided on the interposer substrate; and
a plurality of memory dies stacked on the buffer die,
wherein the buffer die comprises an active layer, the active layer comprising:
a first active pattern provided on a first substrate;
a first device isolation layer provided on the first substrate and configured to define the first active pattern; and
a first gate electrode provided on a channel of the first active pattern,
wherein the channel of the first active pattern is positioned higher than an upper surface of the first device isolation layer.
 
20. A semiconductor package, comprising:
a logic die provided on an interposer substrate;
a buffer die provided on the interposer substrate; and
a plurality of memory dies provided on the buffer die,
wherein the buffer die comprises an active layer including:
a first active pattern provided on a first substrate;
a first device isolation layer provided on the first substrate; and
a first gate electrode provided on a channel of the first active pattern, and
wherein the channel of the first active pattern is positioned higher than an upper surface of the first device isolation layer.