US 11,955,455 B2
Embedded stress absorber in package
Shin-Puu Jeng, Po-Shan Village (TW); Chien-Sheng Chen, Hsinchu (TW); Po-Yao Lin, Zhudong Township (TW); Po-Chen Lai, Hsinchu (TW); and Shu-Shen Yeh, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/814,788.
Application 17/814,788 is a division of application No. 17/149,348, filed on Jan. 14, 2021, granted, now 11,532,593.
Claims priority of provisional application 63/085,222, filed on Sep. 30, 2020.
Prior Publication US 2022/0359457 A1, Nov. 10, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01)
CPC H01L 24/81 (2013.01) [H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 24/96 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
an interconnect structure comprising:
a plurality of dielectric layers; and
a plurality of redistribution lines in the plurality of dielectric layers;
a package component over the interconnect structure, wherein the package component comprises a device die;
a stress absorber over the interconnect structure, wherein the stress absorber has a first Young's modulus; and
an encapsulant on the package component and the stress absorber, wherein the encapsulant has a second Young's modulus greater than the first Young's modulus.