US 11,955,437 B2
Regulator circuit package techniques
Leonard Shtargot, Campbell, CA (US); Zafer Kutlu, Menlo Park, CA (US); and John Underhill Gardner, San Jose, CA (US)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on May 6, 2021, as Appl. No. 17/313,845.
Application 17/313,845 is a division of application No. 16/193,843, filed on Nov. 16, 2018, granted, now 11,037,883.
Prior Publication US 2021/0257313 A1, Aug. 19, 2021
Int. Cl. H01L 23/552 (2006.01); H01L 21/3205 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2023.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H02M 1/08 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 21/32051 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3121 (2013.01); H01L 23/367 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/16 (2013.01); H01L 27/0207 (2013.01); H01L 27/0617 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3025 (2013.01); H02M 1/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming a power converter control circuit package, the method comprising:
mounting an integrated circuit die and at least two passive devices on a substrate, the substrate supporting at least two conductive layers, and wherein a layout defined by locations of the at least two passive devices and electrical interconnections of the two passive devices provided by the substrate to the integrated circuit die are substantially symmetric about at least one axis;
covering an entirety of the at least two passive devices with an encapsulant to provide a panel of encapsulated power converter control packages;
defining an exposed region of the integrated circuit die with the encapsulant; and
electrically coupling at least a portion of the exposed region with a circuit defined by the integrated circuit die.