US 11,955,436 B2
Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission
Khang Choong Yong, Puchong (MY); Ying Ern Ho, Bayan Lepas (MY); Yun Rou Lim, Bayan Lepas (MY); Wil Choon Song, Bayan Lepas (MY); and Stephen Hall, Forest Grove, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 24, 2019, as Appl. No. 16/393,304.
Prior Publication US 2020/0343194 A1, Oct. 29, 2020
Int. Cl. H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H05K 1/02 (2006.01)
CPC H01L 23/552 (2013.01) [H01L 23/66 (2013.01); H01L 24/17 (2013.01); H05K 1/0216 (2013.01); H05K 1/025 (2013.01); H01L 2223/6627 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A package substrate, comprising:
a dielectric over a conductive layer;
a conductive line on the dielectric;
a plurality of conductive bumps on a surface of the conductive line, wherein the plurality of conductive bumps are conductively coupled to the conductive line and are embedded in the dielectric;
a plurality of metal features on the plurality of conductive bumps, wherein individual ones of the plurality of metal features are on a corresponding individual one of the plurality of conductive bumps, and wherein the plurality of metal features has a metal conductivity different than that of the plurality of conductive bumps; and
a solder resist over the conductive line and the dielectric.