US 11,955,422 B2
On-chip capacitors in semiconductor devices and methods for forming the same
Lei Xue, Wuhan (CN); Wei Liu, Wuhan (CN); and Liang Chen, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 28, 2021, as Appl. No. 17/488,287.
Application 17/488,287 is a division of application No. 17/147,409, filed on Jan. 12, 2021, granted, now 11,652,042.
Application 17/147,409 is a continuation of application No. PCT/CN2020/128709, filed on Nov. 13, 2020.
Claims priority of application No. PCT/CN2020/112959 (WO), filed on Sep. 2, 2020; and application No. PCT/CN2020/112962 (WO), filed on Sep. 2, 2020.
Prior Publication US 2022/0068797 A1, Mar. 3, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H01L 23/5223 (2013.01) [H01L 21/76832 (2013.01); H01L 28/40 (2013.01); H01L 28/56 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
at least one dielectric layer pair in contact with the substrate, comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer;
an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair;
one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair;
a memory stack comprising a plurality of conductive/dielectric layer pairs each comprising a conductive layer and the first dielectric layer; and
a plurality of channel structures each extending vertically through the memory stack,
wherein the capacitors include a plurality of first contacts each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair,
the plurality of first contacts are disposed in a peripheral region outside of the memory stack,
the memory stack comprises a staircase structure, and
the semiconductor device further comprises a plurality second contacts each in contact with a respective one of the conductive layers of the memory stack at the staircase structure.