| CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H01L 23/49866 (2013.01); H01L 23/49877 (2013.01)] | 10 Claims |
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1. A method for manufacturing a semiconductor structure, comprising:
forming a via through a substrate from a top surface to a bottom surface of the substrate;
forming a liner layer on a sidewall of the via;
forming a barrier layer on the liner layer using a conductive 2D material; and
forming a conductor in a remaining space of the via;
wherein after forming the conductor, the method further comprises:
patterning the barrier layer and the conductor;
conducting a backside grinding process to expose the via from a backside of the substrate;
sequentially forming a second liner layer, a second barrier layer, and a second conductor on the bottom surface of the substrate; and
patterning the second barrier layer and the second conductor.
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