US 11,955,412 B2
Low stress asymmetric dual side module
Chee Hiong Chew, Seremban (MY); Atapol Prajuckamol, Thanyaburi (TH); Stephen St. Germain, Gilbert, AZ (US); and Yusheng Lin, Phoenix, AZ (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Sep. 6, 2022, as Appl. No. 17/929,898.
Application 17/929,898 is a division of application No. 16/733,322, filed on Jan. 3, 2020, granted, now 11,469,163.
Application 16/733,322 is a continuation in part of application No. 16/678,039, filed on Nov. 8, 2019, granted, now 11,462,515.
Claims priority of provisional application 62/882,119, filed on Aug. 2, 2019.
Prior Publication US 2022/0415767 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/40 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49575 (2013.01) [H01L 23/367 (2013.01); H01L 23/4093 (2013.01); H01L 23/49568 (2013.01); H01L 23/49582 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming semiconductor packages, the method comprising:
providing a first panel of a plurality of first substrates and a second panel of a plurality of second substrates;
printing a first electrically conductive bonding material on a first side of each of the first panel of the plurality of first substrates and a second side of the plurality of second substrates in predetermined locations;
coupling two or more die to each of the first panel of the plurality of first substrates and the second panel of the plurality of second substrates at the predetermined locations;
dispensing a second electrically conductive material onto a second side of each of the two or more die;
coupling a clip to each of the two or more die;
electrically coupling the two or more die to each of the plurality of first substrates and each of the plurality of second substrates;
singulating the first panel and the second panel each into the plurality of first substrates and the plurality of second substrates, respectively;
dispensing solder onto a plurality of predetermined locations on a first side of each of the first substrates and the second substrates;
coupling a first substrate of the plurality of first substrates to a first side of a lead frame; and
coupling a first side of a second substrate of the plurality of second substrates to a second side of the lead frame.