US 11,955,406 B2
Temperature control element utilized in device die packages
Yingying Wang, Sunnyvale, CA (US); Emad Samadiani, Cypress, CA (US); Madhusudan K. Iyengar, Foster City, CA (US); Padam Jain, San Jose, CA (US); Xiaojin Wei, Dublin, CA (US); Teckgyu Kang, Saratoga, CA (US); Sudharshan Sugavanesh Udhayakumar, Santa Clara, CA (US); and Yingshi Tang, Danville, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Jan. 7, 2022, as Appl. No. 17/570,647.
Claims priority of provisional application 63/281,287, filed on Nov. 19, 2021.
Prior Publication US 2023/0163048 A1, May 25, 2023
Int. Cl. H01L 23/46 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/46 (2013.01) [H01L 21/56 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/29035 (2013.01); H01L 2224/32221 (2013.01); H01L 2224/73253 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit (“IC”) package, comprising:
an IC die disposed on a printed circuit board (“PCB”), and
a temperature control element encasing the IC die, wherein the temperature control element comprises:
a plurality of thermal dissipating features disposed on a first surface of the IC die;
a manifold disposed on the PCB encasing the plurality of thermal dissipating features disposed on the IC die; and
a spacer disposed between the plurality of thermal dissipating features and the manifold,
wherein the plurality of thermal dissipating features comprises a metallic pin fin disposed on a solder bump.