US 11,955,399 B2
Semiconductor package
Ae-Nee Jang, Seoul (KR); Seung-Duk Baek, Hwaseong-si (KR); and Tae-Heon Kim, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 21, 2023, as Appl. No. 18/137,803.
Application 18/137,803 is a continuation of application No. 17/340,197, filed on Jun. 7, 2021, granted, now 11,664,292.
Application 17/340,197 is a continuation of application No. 16/507,974, filed on Jul. 10, 2019, granted, now 11,056,414, issued on Jul. 6, 2021.
Claims priority of application No. 10-2018-0125678 (KR), filed on Oct. 22, 2018.
Prior Publication US 2023/0282538 A1, Sep. 7, 2023
Int. Cl. H01L 23/34 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/367 (2013.01) [H01L 23/3157 (2013.01); H01L 23/3738 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/5384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
an interposer located over an upper surface of the package substrate and electrically connected with the package substrate;
a logic chip located over an upper surface of the interposer and electrically connected with the interposer;
a memory chip located over the upper surface of the interposer and electrically connected with the interposer and the logic chip, the memory chip having an upper surface that is higher than an upper surface of the logic chip; and
a heat sink including a first lower surface making thermal contact with the upper surface of the memory chip, and a second lower surface extended downwardly from the first lower surface and making thermal contact with the upper surface of the logic chip to dissipate heat in the memory chip and the logic chip,
wherein the first lower surface of the heat sink is positioned over the upper surface of the memory chip.