US 11,955,395 B2
Fan out package with integrated peripheral devices and methods
Lizabeth Keser, Munich (DE); Bernd Waidhas, Pettendorf (DE); Thomas Ort, Veitsbronn (DE); and Thomas Wagner, Regelsbach (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,674.
Application 17/855,674 is a continuation of application No. 16/894,434, filed on Jun. 5, 2020, granted, now 11,404,339.
Application 16/894,434 is a continuation of application No. 15/938,741, filed on Mar. 28, 2018, granted, now 10,699,980, issued on Jun. 30, 2020.
Prior Publication US 2022/0336306 A1, Oct. 20, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/3114 (2013.01) [H01L 21/568 (2013.01); H01L 23/5226 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/96 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H01L 2224/02379 (2013.01); H01L 2924/19011 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first capacitor device having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall opposite the first sidewall, and the first capacitor device having a lateral width between the first sidewall and the second sidewall;
an encapsulant laterally adjacent to the first capacitor device, a first portion of the encapsulant in contact with the first sidewall of the first capacitor device, and a second portion of the encapsulant in contact with the second sidewall of the first capacitor device;
a second capacitor device laterally spaced apart from the first capacitor device, the second capacitor device in contact with the encapsulant;
an integrated routing layer comprising a plurality of successive dielectric layers and layers of electrical traces, the integrated routing layer on the top side of the first capacitor device, the integrated routing layer on the first portion of the encapsulant, the integrated routing layer on the second portion of the encapsulant, and the integrated routing layer including an electrical trace coupled to the top side of the first capacitor device, the electrical trace extending from a location vertically over the first capacitor device to a location laterally outside of the lateral width of the first capacitor device;
a first solder ball coupled to the electrical trace of the integrated routing layer, the first solder ball vertically above an uppermost one of the plurality of succesive dielectric layers of the integrated routing layer, wherein the first solder ball is not in contact with the uppermost one of the plurality of succesive dielectric layers of the integrated routing layer; and
a second solder ball above and vertically overlapping with the second capacitor device.