US 11,955,389 B2
HVMOS reliability evaluation using bulk resistances as indices
Chia-Chung Chen, Keelung (TW); Chi-Feng Huang, Zhubei (TW); and Tse-Hua Lu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/815,354.
Application 15/995,778 is a division of application No. 14/959,393, filed on Dec. 4, 2015, granted, now 9,991,260, issued on Jun. 5, 2018.
Application 14/959,393 is a division of application No. 13/111,730, filed on May 19, 2011.
Application 17/815,354 is a continuation of application No. 17/072,251, filed on Oct. 16, 2020, granted, now 11,482,459.
Application 17/072,251 is a continuation of application No. 16/599,929, filed on Oct. 11, 2019, granted, now 10,833,082, issued on Nov. 10, 2020.
Application 16/599,929 is a continuation of application No. 15/995,778, filed on Jun. 1, 2018, granted, now 10,504,896, issued on Dec. 10, 2019.
Prior Publication US 2022/0367295 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/66 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); G01R 27/08 (2006.01)
CPC H01L 22/14 (2013.01) [H01L 22/34 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 29/0619 (2013.01); H01L 29/0649 (2013.01); G01R 27/08 (2013.01); H01L 29/1087 (2013.01); H01L 29/7835 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a semiconductor substrate;
a plurality of P-type Metal-Oxide-Semiconductor (PMOS) devices formed at a surface of the semiconductor substrate, wherein the plurality of PMOS devices comprise a row of PMOS devices aligned as a row, and wherein the row of PMOS devices are interconnected in parallel to act as a single PMOS device; and
an n-type guard region adjacent to the plurality of PMOS devices, wherein the n-type guard region comprises portions on two sides of the row, and wherein the n-type guard region comprises:
a first portion on a first side of the plurality of PMOS devices, wherein the first portion is elongated and has a first lengthwise direction parallel to a row direction of the row.