US 11,955,386 B2
Method for evaluating defective region of wafer
Jae Hyeong Lee, Gumi-si (KR)
Assigned to SK Siltron Co., Ltd., Gumi-si (KR)
Appl. No. 17/267,566
Filed by SK SILTRON CO., LTD., Gumi-si (KR)
PCT Filed Dec. 27, 2018, PCT No. PCT/KR2018/016723
§ 371(c)(1), (2) Date Feb. 10, 2021,
PCT Pub. No. WO2020/040364, PCT Pub. Date Feb. 27, 2020.
Claims priority of application No. 10-2018-0096559 (KR), filed on Aug. 20, 2018.
Prior Publication US 2021/0320037 A1, Oct. 14, 2021
Int. Cl. H01L 21/66 (2006.01); G01N 21/88 (2006.01); G01N 21/95 (2006.01); G01N 21/956 (2006.01)
CPC H01L 22/12 (2013.01) [G01N 21/8851 (2013.01); G01N 21/9501 (2013.01); G01N 21/956 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A wafer defect region evaluation method comprising:
preparing a sample wafer;
forming a first oxide film on the sample wafer at a temperature of 700° C. to 800° C.;
forming a second oxide film on the first oxide film at a temperature of 800° C. to 1000° C.;
forming a third oxide film on the second oxide film at a temperature of 1000° C. to 1100° C.;
forming a fourth oxide film on the third oxide film at a temperature of 1100° C. to 1200° C.;
removing the first to fourth oxide films;
etching the sample wafer, from which the first to fourth oxide films are removed, to form haze on a surface of the sample wafer; and
evaluating a defect region of the sample wafer based on the haze.