US 11,955,385 B2
Semiconductor devices with dielectric passivation layer and methods of manufacturing thereof
Shih-Yao Lin, New Taipei (TW); Chih-Han Lin, Hsinchu (TW); Chen-Ping Chen, Toucheng Township (TW); and Hsiao Wen Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,865.
Prior Publication US 2023/0060742 A1, Mar. 2, 2023
Int. Cl. H01L 21/8234 (2006.01); B82Y 10/00 (2011.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/823418 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first stack structure including a first plurality of semiconductor layers vertically spaced from one another;
a second stack structure including a second plurality of semiconductor layers vertically spaced from one another;
a third stack structure including a third plurality of semiconductor layers vertically spaced from one another, wherein the first, second, and third stack structures all extend along a first lateral direction, wherein the second stack structure is disposed between the first and third stack structures along a second lateral direction perpendicular to the first lateral direction; and
a first gate structure that extends along the second lateral direction and wraps around each of the first plurality of semiconductor layers, each of the second plurality of semiconductor layers, and each of the third plurality of semiconductor layers, and
wherein ends of each of the first plurality of semiconductor layers are coupled with respective source/drain structures, ends of each of the second plurality of semiconductor layers are coupled with respective source/drain structures, and ends of each of the third plurality of semiconductor layers are coupled with a dielectric passivation layer.