CPC H01L 21/76898 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76846 (2013.01); H01L 23/481 (2013.01)] | 9 Claims |
1. A manufacturing method of a semiconductor device, comprising:
providing a semiconductor base, wherein a first medium layer is formed on a first surface of the base;
patterning the first medium layer to form a groove extending along the base in the base;
forming a dielectric layer and a first barrier layer sequentially on an inner wall of the groove;
forming a first auxiliary layer and a first metal layer sequentially in the groove, wherein the first metal layer is located on a side of the first auxiliary layer towards the first medium layer, wherein the materials of the dielectric layer and the first auxiliary layer are the same or different;
thinning the base on a second surface of the base to expose the first auxiliary layer;
removing the first auxiliary layer to form a first opening;
forming a second medium layer on the second surface of the base, wherein the second medium layer has a second opening, and the second opening exposes the first opening;
forming a second metal layer on the second surface of the base, wherein the second metal layer fills the first opening;
etching and removing the dielectric layer to form an air gap structure, wherein the air gap structure is a gap between the first barrier layer and the inner wall of the groove;
wherein etching and removing the dielectric layer to form the air gap structure comprises:
etching and removing the dielectric layer in the first medium layer and the groove; and
rapidly depositing a third medium layer on the first surface of the base to form the air gap structure in the groove.
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