	US 11,955,285 B2
	Structure and methods of forming the structure
Tae Heui Kwong, Seoul (KR)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Oct. 9, 2020, as Appl. No. 17/067,587.
Application 17/067,587 is a division of application No. 16/237,341, filed on Dec. 31, 2018, granted, now 10,804,036.
Application 14/790,414 is a division of application No. 13/214,902, filed on Aug. 22, 2011, granted, now 9,082,555.
Application 16/237,341 is a continuation of application No. 15/948,740, filed on Apr. 9, 2018, granted, now 10,170,248.
Application 15/948,740 is a continuation of application No. 15/676,597, filed on Aug. 14, 2017, granted, now 9,941,053.
Application 15/676,597 is a continuation of application No. 14/790,414, filed on Jul. 2, 2015, granted, now 9,734,949.
Prior Publication US 2021/0098196 A1, Apr. 1, 2021
Int. Cl. H01G 4/30 (2006.01); H01G 4/005 (2006.01); H01G 4/06 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01)

CPC H01G 4/30 (2013.01) [H01G 4/005 (2013.01); H01G 4/06 (2013.01); H01L 23/52 (2013.01); H01L 23/522 (2013.01); H01L 23/535 (2013.01); Y10T 29/43 (2015.01)]

10 Claims

1. A method of forming a memory structure, comprising:

forming a three-dimensional (3D) memory cell region; and

forming a peripheral region adjacent to the memory cell region, including forming a capacitor structure including multiple conductive levels separated by dielectric levels, comprising:

forming a first conductive level, a second conductive level above the first conductive level, and a third conductive level above the second conductive level;

wherein the second conductive level is stepped back from an upper surface end portion of the first conductive level, and wherein the third conductive level is stepped back from an upper surface end portion of the second conductive level;

wherein the first and second conductive levels are separated by a first dielectric level, and wherein the second and third conductive levels are separated by a second dielectric level.