US 11,955,201 B2
Memory device
Meng-Sheng Chang, Hsinchu County (TW); Chia-En Huang, Hsinchu County (TW); Yi-Ching Liu, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,692.
Application 17/873,692 is a continuation of application No. 17/085,398, filed on Oct. 30, 2020, granted, now 11,423,960.
Prior Publication US 2022/0358976 A1, Nov. 10, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01); G11C 8/14 (2006.01)
CPC G11C 7/1051 (2013.01) [G11C 7/1006 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of arrays coupled in parallel with each other, wherein a first array of the plurality of arrays comprises:
a first switch and a plurality of first memory cells that are arranged in a first column;
a second switch and a plurality of second memory cells that are arranged in a second column; and
first and second data lines that are coupled to the plurality of first memory cells and the plurality of second memory cells,
wherein the second switch is configured to output a data signal from the second data line to a sense amplifier,
wherein control terminals of the first switch and the second switch are coupled together to a control line
wherein first portions of the first and second data lines extend in a row direction below the first and second switches, and
the plurality of first and second memory cells are arranged between the first portions of the first and second data lines and the first to second switches.