US 11,955,195 B2
Semiconductor memory device with defect detection capability
Seongkyung Kim, Hwaseong-si (KR); Dahye Min, Suwon-si (KR); and Ukjin Jung, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 19, 2022, as Appl. No. 17/748,441.
Claims priority of application No. 10-2021-0132672 (KR), filed on Oct. 6, 2021.
Prior Publication US 2023/0104520 A1, Apr. 6, 2023
Int. Cl. G11C 11/412 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/50 (2013.01) [G11C 11/412 (2013.01); G11C 2029/5004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate that comprises a memory cell region and a test region;
an active pattern on the memory cell region;
a source/drain pattern on the active pattern;
a dummy pattern on the test region;
a first gate electrode that extends in a first direction on the dummy pattern;
a first common contact in contact with the dummy pattern and the first gate electrode; and
a first wiring layer on the first common contact,
wherein the first wiring layer comprises a first test line electrically connected to the first common contact,
wherein the first common contact comprises:
a first contact pattern in contact with the dummy pattern; and
a first gate contact electrically connected to the first gate electrode,
wherein the first gate contact comprises:
a body part coupled to the first gate electrode; and
a protrusion part that extends from the body part and into the first contact pattern, and
wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.