CPC G11C 29/42 (2013.01) [G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 29/12015 (2013.01); G11C 29/44 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
responsive to detecting a triggering event, randomly selecting, from a subset of memory blocks of the memory device, a set of memory cells, wherein the subset of memory blocks is associated with a first bin of read voltage offsets (RVOs) of a plurality of bins of RVOs, and wherein the first bin of RVOs is associated with a first set of RVOs applied to memory cells during read operations;
applying, to the set of memory cells, a first set of calibration read operations using the first bin of RVOs;
applying, to the set of memory cells, a second set of calibration read operations using a second bin of RVOs of the plurality of bins of RVOs;
selecting, based on at least the first set of calibration read operations and the second set of calibration read operations, a target bin of RVOs from a group comprising the first bin of RVOs and the second bin of RVOs; and
associating the subset of memory blocks with the target bin of RVOs.
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