CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/20 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a plurality of one-time-programmable (OTP) memory cells;
wherein each of the plurality of OTP memory cells comprises N first transistors, N second transistors, N third transistors, N diode-connected transistors, and a capacitor, N being a positive integer; and
wherein each of the N first transistors is coupled to a respective one of the N second transistors, a respective one of the N third transistors, and a respective one of the M diode-connected transistors in series, with one terminal of the capacitor connected to a node between the respective second transistor and the respective third transistor.
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