| CPC G11C 16/3445 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01)] | 13 Claims |
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1. A semiconductor storage device comprising:
a memory block including a plurality of memory strings, a first control signal line, a plurality of second control signal lines, a third control signal line, and a plurality of bit lines, the plurality of memory strings each including a first select gate transistor, a plurality of memory cell transistors, and a second select gate transistor that are connected in series, the first control signal line being connected to a gate of the first select gate transistor of each of the plurality of memory strings in common, the plurality of second control signal lines each being connected to gates of the memory cell transistors of the plurality of memory strings on a corresponding row in common, the third control signal line being connected to a gate of the second select gate transistor of each of the plurality of memory strings in common, the plurality of bit lines being connected to the plurality of memory strings;
a resistance measurement circuit configured to measure resistance of at least one control signal line among the first control signal line, the second control signal lines, and the third control signal line; and
a control circuit configured to perform erase, program, and read of data at the plurality of memory cell transistors included in the memory block, wherein
the control circuit determines, based on a measurement result of the resistance measurement by the resistance measurement circuit, whether to set a fail status to a result of erase verify that verifies the erase.
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