| CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/3459 (2013.01)] | 12 Claims |
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1. A memory device comprising:
a memory block including a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines;
a peripheral circuit configured to perform a first program operation and a second program operation on the memory block; and
a control logic configured to control the program operation of the peripheral circuit,
wherein the memory block is connected to first to n-th word lines,
wherein the control logic is configured to control the peripheral circuit to perform the first program operation on a physical page, among a plurality of physical pages that are included in a first string group, connected to the i-th word line, perform the second program operation on a physical page that is connected to the (i−1)-th word line, perform the first program operation on a physical page, among a plurality of physical pages that are included in a second string group, connected to the (i+1)-th word line, perform a dummy program operation on a physical page, among the plurality of physical pages that are included in the first string group, connected to the (i+1)-th word line, perform the second program operation on the physical page that is connected to the i-th word line, perform the dummy program operation on a physical page, among the plurality of physical pages that are included in the second string group, connected to the (i+1)-th word line, and perform the second program operation on the physical page that is connected to the i-th word line, and
wherein n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n−1.
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