US 11,955,179 B2
Semiconductor memory device
Yuki Inuzuka, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 29, 2022, as Appl. No. 17/853,555.
Claims priority of application No. 2022-002327 (JP), filed on Jan. 11, 2022.
Prior Publication US 2023/0223081 A1, Jul. 13, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate having a substrate surface extending in a first direction and a second direction crossing the first direction;
a first memory pillar extending in a third direction from the substrate surface, the first memory pillar including
a plurality of first memory cell transistors electrically connected in series with each other, and the first memory cell transistors having a first end and a second end,
a first selection transistor electrically connected to the first end,
a second selection transistor electrically connected to the second end,
a plurality of second memory cell transistors electrically connected in series with each other, the second memory cell transistors having a third end and a fourth end, and the second memory cell transistors being electrically insulated from the first memory cell transistors,
a third selection transistor electrically connecting the first selection transistor and the third end,
a fourth selection transistor electrically connecting the second selection transistor and the fourth end,
a plurality of third memory cell transistors electrically connected in series with each other, and the third memory cell transistors having a fifth end and a sixth end,
a fifth selection transistor electrically connecting the second selection transistor, the fourth selection transistor and the fifth end,
a sixth selection transistor electrically connected to the sixth end,
a plurality of fourth memory cell transistors electrically connected in series with each other, the fourth memory cell transistors having a seventh end and an eighth end, and the fourth memory cell transistors being electrically insulated from the third memory cell transistors,
a seventh selection transistor electrically connecting the second selection transistor, the fourth selection transistor, the fifth selection transistor and the seventh end, and
an eighth selection transistor electrically connecting the sixth selection transistor and the eighth end;
a first select gate line provided above the substrate to extend in parallel to the substrate surface, the first select gate line facing a first side of the first memory pillar, and the first select gate line being electrically connected to a gate of the first selection transistor;
a plurality of first word lines provided above the first select gate line to extend in parallel to the substrate surface, the first word lines facing the first side of the first memory pillar, and the first word lines being electrically connected to gates of the first memory cell transistors, respectively;
a second select gate line provided above the first word lines to extend in parallel to the substrate surface, the second select gate line facing the first side of the first memory pillar, and the second select gate line being electrically connected to a gate of the second selection transistor;
a third select gate line provided above the substrate to extend in parallel to the substrate surface, a position of the third select gate line in the third direction being the same as a position of the first select gate line in the third direction, the third select gate line facing a second side of the first memory pillar, and the third select gate line being electrically connected to a gate of the third selection transistor;
a plurality of the second word lines provided above the third select gate line to extend in parallel to the substrate surface, a position of the second word lines in the third direction being the same as a position of the first word lines in the third direction, respectively, the second word lines facing the second side of the first memory pillar, and the second word lines being electrically connected to gates of the second memory cell transistors, respectively;
a fourth select gate line provided above the second word lines to extend in parallel to the substrate surface, a position of the fourth select gate line in the third direction being the same as a position of the second select gate line in the third direction, the fourth select gate line facing the second side of the first memory pillar, and the fourth select gate line being electrically connected to a gate of the fourth selection transistor;
a fifth select gate line provided above the substrate to extend in parallel to the substrate surface, the fifth select gate line facing the first side of the first memory pillar, and the fifth select gate line being electrically connected to a gate of the fifth selection transistor;
a plurality of third word lines provided above the fifth select gate line to extend in parallel to the substrate surface, the third word lines facing the first side of the first memory pillar, and the third word lines being electrically connected to a gate of the third memory cell transistor and the first word lines, respectively;
a sixth select gate line provided above the third word lines to extend in parallel to the substrate surface, the sixth select gate line facing the first side of the first memory pillar, and the sixth select gate line being electrically connected to the sixth selection transistor;
a seventh select gate line provided above the substrate to extend in parallel to the substrate surface, a position of the seventh select gate line in the third direction being the same as a position of the fifth select gate line, the seventh select gate line facing the second side of the first memory pillar, and the seventh select gate line being electrically connected to a gate of the seventh selection transistor;
a plurality of fourth word lines provided above the seventh select gate line to extend in parallel to the substrate surface, a position of the fourth word lines in the third direction being the same as a position of the third word lines, respectively, the fourth word lines facing the second side of the first memory pillar, and the fourth word lines being electrically connected to the second word lines and the gates of the fourth memory cell transistors, respectively; and
an eighth select gate line provided above the fourth word lines to extend in parallel to the substrate surface, a position of the eighth select gate line in the third direction being the same as a position of the sixth select gate line, the eighth select gate line facing the second side of the first memory pillar, and the eighth select gate line being electrically connected to a gate of the eighth selection transistor.