US 11,955,178 B2
Information processing apparatus and memory system
Atsushi Kawasumi, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 15, 2022, as Appl. No. 17/695,278.
Claims priority of application No. 2021-152618 (JP), filed on Sep. 17, 2021.
Prior Publication US 2023/0090235 A1, Mar. 23, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information processing apparatus comprising:
a plurality of strings connected to a first wiring and connected to a plurality of second wirings, wherein
the string has one end connected to the first wiring and includes a plurality of transistors being connected to each other, each of gates of the plurality of transistors being connected to corresponding one of the second wirings,
the plurality of transistors include a first transistor and a second transistor, the first transistor being set to a first threshold according to first data, and the second transistor being set to a second threshold according to second data in a complement relationship with the first data,
two second wirings of the plurality of second wirings are connected to gates of the first transistor and the second transistor, and
one of the two second wirings is set to a potential level corresponding to third data, and another of the two second wirings is set to a potential level corresponding to fourth data in a complement relationship with the third data.