| CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a memory array of a plurality of memory elements, each of the memory elements comprising two memory cells;
a plurality of word lines or a plurality of word line pairs connected to rows of the memory array;
a plurality of bit line pairs connected to columns of the memory array; and
a plurality of common source lines connected to the columns of the memory array;
wherein the memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.
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