US 11,955,155 B2
Nonvolatile memory device and latch including the same
Seong Ook Jung, Seoul (KR); Se Keon Kim, Seoul (KR); Tae Woo Oh, Seoul (KR); Se Hee Lim, Seoul (KR); and Dong Han Ko, Seoul (KR)
Assigned to UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY, Seoul (KR)
Filed by UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed on Jan. 28, 2022, as Appl. No. 17/588,180.
Claims priority of application No. 10-2021-0018040 (KR), filed on Feb. 9, 2021; and application No. 10-2021-0018041 (KR), filed on Feb. 9, 2021.
Prior Publication US 2022/0254398 A1, Aug. 11, 2022
Int. Cl. G11C 11/22 (2006.01); G11C 7/10 (2006.01); H03K 19/017 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 7/1039 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); H03K 19/01742 (2013.01); H03K 19/20 (2013.01)] 44 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a first inverter;
a second inverter cross-coupled to the first inverter; and
a nonvolatile memory circuit,
wherein the nonvolatile memory circuit includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor (FeFET) of which a first electrode and a second electrode are respectively connected to the pull-up transistor and the pull-down transistor, and wherein when the ferroelectric field effect transistor is programmed to a low resistance state, an equivalent resistance of a current path including the pull-down transistor is smaller than an equivalent resistance of a current path including the pull-up transistor.