US 11,955,153 B1
Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 15, 2022, as Appl. No. 17/654,908.
Application 17/654,908 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
Int. Cl. G11C 11/16 (2006.01); G11C 11/22 (2006.01); H01L 25/065 (2023.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01); H10B 53/00 (2023.01)
CPC G11C 11/161 (2013.01) [G11C 11/221 (2013.01); H01L 25/0652 (2013.01); H01L 28/55 (2013.01); H01L 28/75 (2013.01); H10B 12/20 (2023.02); H10B 12/48 (2023.02); H10B 53/00 (2023.02)] 27 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and
a plurality of memory elements having a first terminal coupled to the storage node, wherein a second terminal of an individual memory element of the plurality of memory elements is coupled to an individual plate-line, and wherein the plurality of memory elements are planar memory elements that are arranged in a stacked and folded configuration.