US 11,955,090 B2
Buffer circuit including offset blocking circuit and display device including the same
Sungho Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 1, 2022, as Appl. No. 17/683,775.
Claims priority of application No. 10-2021-0070193 (KR), filed on May 31, 2021; and application No. 10-2021-0097187 (KR), filed on Jul. 23, 2021.
Prior Publication US 2022/0383823 A1, Dec. 1, 2022
Int. Cl. G09G 3/3275 (2016.01); H03F 3/45 (2006.01)
CPC G09G 3/3275 (2013.01) [H03F 3/45269 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0204 (2013.01); G09G 2330/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A buffer circuit comprising:
an operational amplifier configured to amplify an input voltage to generate an output voltage;
a slew-rate compensating circuit including a boosting transistor, the slew-rate compensating circuit configured to generate a compensation current based on a difference between a voltage level of the input voltage and a voltage level of the output voltage and provide the compensation current to the operational amplifier through the boosting transistor; and
an offset blocking circuit configured to turn off the boosting transistor in response to the difference between the voltage level of the input voltage and the voltage level of the output voltage being less than a reference voltage level by providing a blocking current to a gate of the boosting transistor.