US 11,955,088 B2
Display substrate and display apparatus
Lu Bai, Beijing (CN); Yang Zhou, Beijing (CN); Yi Qu, Beijing (CN); Chang Luo, Beijing (CN); Huijuan Yang, Beijing (CN); Yi Zhang, Beijing (CN); and Junxiu Dai, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Dec. 21, 2022, as Appl. No. 18/086,524.
Application 18/086,524 is a continuation in part of application No. PCT/CN2021/124137, filed on Oct. 15, 2021.
Prior Publication US 2023/0126436 A1, Apr. 27, 2023
Int. Cl. G09G 3/3266 (2016.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3266 (2013.01) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate, comprising a display region and a peripheral region located at a periphery of the display region;
a plurality of sub-pixels, located in the display region;
a plurality of first gate drive circuits and at least one auxiliary structure, which are located in the peripheral region; wherein
the plurality of first gate drive circuits are configured to provide a first gate drive signal for the plurality of sub-pixels;
the at least one auxiliary structure is disposed between adjacent first gate drive circuits;
the at least one auxiliary structure comprises: at least one first auxiliary structure;
a first auxiliary structure is located between a first gate drive circuit in n-th stage and a first gate drive circuit in (n−1)-th stage, the first gate drive circuit in the n-th stage and the first gate drive circuit in the (n−1)-th stage are not cascaded;
the first gate drive circuit in the n-th stage is electrically connected to a first start signal line through the first auxiliary structure, where n is an integer;
the first auxiliary structure comprises: a first auxiliary semiconductor block, a first connection electrode, and a second connection electrode; and
the first auxiliary semiconductor block is electrically connected to an output terminal of the first gate drive circuit in the n-th stage and the second connection electrode, the second connection electrode is electrically connected to the first connection electrode, and the first connection electrode is electrically connected to the first start signal line.