| CPC G06N 3/063 (2013.01) | 20 Claims |
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1. A neural processing unit (NPU) comprising:
a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator;
a clock signal supply circuitry configured to output one or more clock signals; and
a second circuitry configured to process a plurality of feature maps outputted from the plurality of PEs,
wherein when the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, is supplied to the first group of PEs and a second clock signal among the one or more clock signals, is supplied to the second group of PEs,
wherein at least one of the first and second clock signals has a preset phase based on a phase of an original clock signal, and
wherein the second circuitry processes one or more first feature maps from the first group of PEs and one or more second feature maps from the second group of PEs in a first input first output (FIFO) manner.
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