US 11,954,582 B2
Neural network accelerator
Sungju Ryu, Busan (KR); Hyungjun Kim, Pohang-si (KR); and Jae-Joon Kim, Pohang-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 21, 2022, as Appl. No. 18/085,939.
Application 18/085,939 is a continuation of application No. 16/868,845, filed on May 7, 2020, granted, now 11,562,218.
Claims priority of application No. 10-2019-0070884 (KR), filed on Jun. 14, 2019.
Prior Publication US 2023/0131035 A1, Apr. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/485 (2006.01); G06F 7/523 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/485 (2013.01); G06F 7/523 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural network accelerator comprising:
a first bit operator configured to generate first product bits of a multiplication of first feature bits of first input feature data and first weight bits of first weight data;
a second bit operator configured to generate second product bits of a multiplication of first feature bits of second input feature data and first weight bits of second weight data;
a first adder configured to generate first sum bits, including a summation of the first product bits and the second product bits; and
a first shifter configured to generate a first bit-shifted value by first bit-shifting the first sum bits by a first bit shift extent for generating output feature data,
wherein the first bit shift extent is dependent on a first bit position difference between a least significant bit of the first feature bits, in the first input feature data, and a least significant bit of the first input feature data, and the first bit shift extent is dependent on a second bit position difference between a least significant bit of the first weight bits, in the first weight data, and a least significant bit of the first weight data.