US 11,954,499 B2
Operational code storage for an on-die microprocessor
Troy A. Manning, Meridian, ID (US); Jonathan D. Harms, Meridian, ID (US); Troy D. Larsen, Meridian, ID (US); Glen E. Hush, Boise, ID (US); and Timothy P. Finkbeiner, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 10, 2022, as Appl. No. 17/885,143.
Application 17/885,143 is a continuation of application No. 16/878,226, filed on May 19, 2020, granted, now 11,422,826.
Prior Publication US 2023/0033704 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/4401 (2018.01); G06F 9/38 (2018.01); G06F 12/0868 (2016.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01)
CPC G06F 9/4403 (2013.01) [G06F 9/3836 (2013.01); G06F 9/4406 (2013.01); G06F 12/0868 (2013.01); G06F 12/1054 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7211 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a microprocessor;
a set of memory arrays coupled with the microprocessor; and
a bus operable to receive data from an external source, wherein:
a first subset of memory cells of the set of memory arrays are configured to store data received via the bus; and
a second subset of memory cells of the set of memory arrays are configured to store at least two copies of instructions executable by the microprocessor.