US 11,954,465 B2
Apparatuses, methods, computer programs, and data carriers for indicating and detecting atomic operations
Alexei Katranov, Nizhny Novgorod (RU); and Stanislav Bratanov, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 13, 2021, as Appl. No. 17/643,856.
Prior Publication US 2023/0185547 A1, Jun. 15, 2023
Int. Cl. G06F 8/41 (2018.01); G06F 8/53 (2018.01); G06F 9/30 (2018.01)
CPC G06F 8/41 (2013.01) [G06F 8/53 (2013.01); G06F 9/30094 (2013.01); G06F 9/30032 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one interface configured to read one or more high-level code instructions; and
at least one processor configured to
read the one or more high-level code instructions using the interface,
determine atomic operations in the high-level code instructions, and
translate the one or more high-level code instructions into assembly code instructions, wherein atomic operations are indicated in the assembly code instructions based on the atomic operations in the high-level code instruction,
wherein the at least one processor is configured to indicate the atomic operations in the assembly code instructions using information that is ignored by a processor architecture for which the assembly code instructions are translated,
wherein the at least one processor is configured to indicate the atomic operations in the assembly code instructions by:
i) using meta information, wherein the meta information is ineffective on a result of an execution of the assembly code instructions;
ii) using instruction prefixes that do not affect a result of an instruction execution;
iii) using distinguishable code patterns to mark atomic memory operations;
iv) using excessive segment prefixes;
v) using a one-byte prefix before an atomic instruction in the assembly code instructions; or
vi) using a duplicated segment prefix that atomic operations use or imply.