CPC G06F 7/556 (2013.01) [G06F 7/4873 (2013.01); G06F 7/727 (2013.01)] | 20 Claims |
1. A binary logic circuit for determining the ratio x/d where x is a variable integer input of w bits comprising M>8 blocks of bit width r≥1 bit, and d>2 is a fixed integer, the binary logic circuit comprising:
a logarithmic tree of modulo units each configured to calculate x[a: b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M−1}, and, on the basis that any given modulo unit introduces a delay of 1, all of the modulo units are arranged in the logarithmic tree within a delay envelope of [log2 M]; and
output logic configured to combine the outputs provided by the subset of M−1 modulo units with blocks of the input x so as to yield the ratio x/d;
wherein the total number of modulo units T in the logarithmic tree for a given number of blocks M is in accordance with the following table:
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||