| CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0613 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A memory system connectable to a host, the memory system comprising:
a plurality of memory chips operable in parallel, each memory chip of the plurality of memory chips including a plurality of first storage areas;
a memory controller configured to:
generate a plurality of first groups, each first group of the plurality of first groups including first storage areas selected from different memory chips among the plurality of memory chips,
generate a plurality of second groups, each second group of the plurality of the second group being constituted by a minimum number of first storage areas composed by excluding one or more first storage areas from each first group of the plurality of first groups, the minimum number of first storage areas being capable of storing at least a first amount of data received from the host, and
execute writing of the data to all the minimum number of first storage areas constituting one second group; and
a circuit configured to execute error correction including encoding data written to each second group by an encoding system whose code rate is variable, and decoding data read from each second group,
wherein the memory controller is configured to:
reduce a code rate of data written to a first second group of the plurality of second groups, and
add at least one of second storage areas to the first second group when a second amount becomes smaller than the first amount due to reduction of the code rate, the second storage areas each being the first storage area excluded from any first group of the plurality of first groups, the second amount indicating a storage capacity of the first second group capable of storing data received from the host.
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